1. Field of the Invention
The present invention generally relates to a semiconductor device and a layout method of the semiconductor device.
2. Description of the Related Art
Recently, demands for reducing the size of the semiconductor chip, higher integration of components in the semiconductor chip, and higher performance of the semiconductor chip have become very significant. In response to the demands, the surface amount technology as a packaging technique that satisfies the demands has become more and more important. As the surface amount technology, much attention is attracted to the BGA (Ball Grid Array), the CSP (Chip Size Package), the WL-CSP (Wafer-Level Chip Size Package) and the like. In the BGA, solder balls are in contact with a printed circuit without using lead frames. In the CSP, the package size is substantially equal to the chip size. Further, the CSP is adopted to achieve downsizing and higher performance. The WL-CSP is described in, for example, Japanese Patent No. 3808030 and Japanese Patent Application Publication No. 2000-299406.
The WL-CSP is manufactured by performing a rewiring process, a metal post forming process, a resin sealing process, a ball forming process and the like on a surface of a wafer that has been manufactured through an LSI (Large Scale Integration) manufacturing process.
FIG. 1 is a schematic cross-sectional view illustrating a part of the WL-CSP. With reference to FIG. 1, a method of manufacturing the WL-CPS is described.
First, a base insulation layer 3 is formed on a semiconductor substrate 1. After elements (devices) (not shown) including active devices (e.g., transistors) and passive devices (e.g., resistors and capacitors) are formed, a base insulation layer 5 including a BPSG (borophosphosilicate glass) film or the like is formed on the entire surface of the semiconductor substrate 1. After forming connection holes (not shown) through the base insulation layer 5, for example, Al wirings (not shown) made of Al (Aluminum) and an Al electrode pad 7 are formed on the base insulation layer 5.
Further, a passivation film 9 having, for example, a PSG (phosphosilicate glass) as a lower layer and an SiN (silicon nitride) as an upper layer is formed on the entire surface of the semiconductor substrate 1. Further, a polyimide layer 11 is formed on the passivation film 9. Then, a pad opening 13 is formed in the insulation layer on the Al electrode pad 7. This is because the Al electrode pad 7 can establish an electrical contact with a metal wiring layer formed in the back-end process (later) and a probe needle is in contact with the electrode pad 7 in a wafer test performed in the back-end process.
Namely, the wafer test is performed by causing the probe needle to make contact with the Al electrode pad 7.
Then, a sputtering method is performed to form a barrier metal layer 15 made of Cr (Chrome) and an electrode layer (not shown) made of Cu (Copper) for plating on the entire surface of the semiconductor substrate 1. The barrier metal layer 15 is formed between a metal wiring layer made of Cu and formed between the back-end process and the Al electrode pad 7 so as to prevent Cu and Al from intruding into each other.
A photoresist pattern is formed on a predetermined region on the electrode layer for plating, and an electrolytic plating is performed to form a Cu wiring layer 17 and a Cu electrode pad 19. The Cu wiring layer 17 and the Cu electrode pad 19 may be called rewiring layers. As the material of the rewiring layers, Cu is generally used to ensure the reliability due to higher mechanical strength, higher moisture resistance and the like.
After removing the photoresist pattern, a wet etching is performed to remove unnecessary electrode layer for plating and the barrier metal layer 15 by using the Cu wiring layer 17 and the Cu electrode pad 19 as a mask. Then, the sputtering method and an electrolytic plating method are performed to form a metal layer. Further, a patterning is performed on the metal layer using a photoengraving technique and an etching technique to form a metal post 21 on the Cu electrode pad 19.
Then, the wafer, a sealing resin, and a temporary film are disposed in a mold for resin sealing, and heated and pressed in a manner such that the metal post 21 appears on the surface of the sealing resin 23. The temporary film herein is the material to prevent the resin from being in contact with the mold.
After forming a barrier metal layer 25 on the surface of the metal post 21, a solder ball 27 is mechanically adhered to the metal post 21 via the barrier metal layer 25, the metal post 21 being formed on the wafer sealed by the sealing resin 23.
After that, the wafer is cut into chips.
By the resin sealing in a wafer level, the number of processes is reduced and the downsizing of the chips is achieved.